From LaurenceWood at SunyataSystems.Com Sat Dec 1 14:56:59 2001 From: LaurenceWood at SunyataSystems.Com (Laurence F. Wood) Date: Sat Dec 3 00:52:11 2005 Subject: [info-cscheme] [bug-cscheme] MIT Scheme 7.6.0 on Windows XP professional In-Reply-To: Message-ID: Thanks for the email. It would seem to me that this AMD chip issue (like the old Intel floating point microcode problem) could affect other machine critical applications. I have passed the information on to a company that does a lot of work with building machines using AMD processors and explained why this needs to be resolved, (I copied Chris's response to them). Since we are purchasing a large number of the systems with the AMD affected chips hopefully this will motivate them to help resolve this with AMD. ============================================ Laurence F. Wood Chief Science Officer Sunyata Systems Corporation 732.701.9746 Direct 732.701.9748 Fax WWW.SUNYATASYSTEMS.COM "Precision Drug Design" -----Original Message----- From: Guillermo J. Rozas [mailto:gjr@zurich.ai.mit.edu] Sent: Saturday, December 01, 2001 2:42 PM To: LaurenceWood@sunyatasystems.com Cc: cph@zurich.ai.mit.edu; info-cscheme@zurich.ai.mit.edu Subject: Re: [info-cscheme] [bug-cscheme] MIT Scheme 7.6.0 on Windows XP professional | From: "Laurence Wood" | Subject: RE: [info-cscheme] [bug-cscheme] MIT Scheme 7.6.0 on Windows XP professional | Date: Fri, 30 Nov 2001 08:52:27 -0500 | | Hi Chris, does this problem relate to just the 7.6.0 version of MIT Scheme | or are all version affected to your knowledge? An I/D cache coherence issue of this sort should affect all versions of MIT Scheme for the x86, unless you forego compiled code completely, which is not a realistic option. It may be an outright I/D cache coherence issue, or a buffering/prefetching issue. Writes may be buffered on their way to the D-cache and hence not participate in the coherence protocol until they reach the D-cache. Similarly instruction prefetch can read the bytes out of the I-cache before the coherence mechanism has had a chance to invalidate them in the I-cache. The 2nd issue is well known in the x86 architecture, and jump instructions are supposed to take care of it. However, the first (write buffering) may be an overlooked aspect of a new microarchitecture. A thing to try would be to use a serializing instruction between any potential writes to instructions (MIT Scheme knows when it is doing this since it has to maintain explicit coherence for other architectures). I don't know which x86 instructions guarantee on the Athlon that the write buffers are drained to the D-cache, however. AMD should be contacted to explore the problem and find a workaround, etc. From gjr at zurich.ai.mit.edu Sat Dec 1 14:41:48 2001 From: gjr at zurich.ai.mit.edu (Guillermo J. Rozas) Date: Sat Dec 3 00:52:11 2005 Subject: [info-cscheme] [bug-cscheme] MIT Scheme 7.6.0 on Windows XP professional In-Reply-To: References: Message-ID: | From: "Laurence Wood" | Subject: RE: [info-cscheme] [bug-cscheme] MIT Scheme 7.6.0 on Windows XP professional | Date: Fri, 30 Nov 2001 08:52:27 -0500 | | Hi Chris, does this problem relate to just the 7.6.0 version of MIT Scheme | or are all version affected to your knowledge? An I/D cache coherence issue of this sort should affect all versions of MIT Scheme for the x86, unless you forego compiled code completely, which is not a realistic option. It may be an outright I/D cache coherence issue, or a buffering/prefetching issue. Writes may be buffered on their way to the D-cache and hence not participate in the coherence protocol until they reach the D-cache. Similarly instruction prefetch can read the bytes out of the I-cache before the coherence mechanism has had a chance to invalidate them in the I-cache. The 2nd issue is well known in the x86 architecture, and jump instructions are supposed to take care of it. However, the first (write buffering) may be an overlooked aspect of a new microarchitecture. A thing to try would be to use a serializing instruction between any potential writes to instructions (MIT Scheme knows when it is doing this since it has to maintain explicit coherence for other architectures). I don't know which x86 instructions guarantee on the Athlon that the write buffers are drained to the D-cache, however. AMD should be contacted to explore the problem and find a workaround, etc. From cph at zurich.ai.mit.edu Mon Dec 17 17:19:20 2001 From: cph at zurich.ai.mit.edu (Chris Hanson) Date: Sat Dec 3 00:52:11 2005 Subject: [info-cscheme] followup on problem with AMD processors Message-ID: There's been some real progress made on fixing the problem running MIT Scheme on AMD processors. Thanks to the efforts of several people, AMD has been involved in this process. The current status is that AMD agrees that there is a bug in the Athlon model 1, Athlon model 4, and Duron model 3 processors. The bug is that these processors don't properly execute self-modifying code of the kind used by MIT Scheme. Other AMD processors, the Athlon model 2, Athlon MP model 6, Mobile Athlon model 6, and Duron model 7, don't exhibit this bug. The other thing that has happened is that I've discovered that appropriate use of an explicit serialization instruction (the CPUID instruction) allows MIT Scheme to work on the buggy processors, although with a performance penalty. I've incorporated conditional use of this instruction into MIT Scheme, and the next release, 7.6.1, will have this support. Unfortunately, this support has a small time penalty on processors that do not have the bug, about 2.4% on the Pentium III I've been benchmarking on. But this seems to me an acceptable price in order to have the code work on all processors. I'm not sure when the next release will occur. I am working on some other changes. But probably early next month.